Logic synthesis tools generate a data flow graph (DFG), which is a graphical representation of a circuit design described by register-transfer level (RTL) code. A DFG includes nodes that represent circuit elements to execute the RTL code. Functions in RTL code correspond to a respective set of nodes in the DFG. However, based on semantics in the RTL code, one or more of those nodes may be unnecessary. Manually examining a DFG to identify unnecessary nodes and revising the corresponding RTL code to generate a DFG without the unnecessary nodes is error prone and unwieldy. The revised RTL code is difficult to maintain and becomes “bloated” with extra lines of code and definitions.